Saturday, November 6, 2010

Sunday Suspense!!!



http://loveukolkata.blogspot.com/2010/11/sunday-suspense-aaro-notun-10-ta.html?utm_source=feedburner&utm_medium=feed&utm_campaign=Feed%3A+loveukolkata%2Fcom+%28Love+U+Kolkata%29
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Sunday Suspense!!!



http://loveukolkata.blogspot.com/2010/11/sunday-suspense-aaro-notun-10-ta.html?utm_source=feedburner&utm_medium=feed&utm_campaign=Feed%3A+loveukolkata%2Fcom+%28Love+U+Kolkata%29
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দীপাবলীর প্রীতি ও শুভেচ্ছা
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Friday, November 5, 2010

VHDL codes 

down counter



library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;


entity counter is 
  port(C, S : in  std_logic; 

        Q : out std_logic_vector(3 downto 0)); 
end counter;
architecture archi of counter is 
  signal tmp: std_logic_vector(3 downto 0); 
  begin 
    process (C) 

      begin 
        if (C'event and C='1') then 
          if (S='1') then
            tmp = "1111"; 

          else 
            tmp = tmp - 1; 
          end if; 
        end if; 
    end process; 

    Q = tmp; 
end archi;


Down Counter Testbench:
                                                                    
                                                                   
                                                                   

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY downtest IS
END downtest;

ARCHITECTURE behavior OF downtest IS

   -- Component Declaration for the Unit Under Test (UUT)

   COMPONENT counter
   PORT(
        C : IN  std_logic;
        S : IN  std_logic;
        Q : OUT  std_logic_vector(3 downto 0)
       );
   END COMPONENT;
  

  --Inputs
  signal C : std_logic := '0';
  signal S : std_logic := '0';

 --Outputs
  signal Q : std_logic_vector(3 downto 0);
  -- No clocks detected in port list. Replace  below with
  -- appropriate port name

BEGIN

 -- Instantiate the Unit Under Test (UUT)
  uut: counter PORT MAP (
         C => C,
         S => S,
         Q => Q
       );

  -- Clock process definitions


  -- Stimulus process
  stim_proc: process
  begin  
     -- hold reset state for 100 ns.
     wait for 100 ns; 
  C<='0';
  S<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  S<='1';
  up_down<='1';
  wait for 100 ns; 
  C<='0';
  S<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  S<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  



   

     -- insert stimulus here

     wait;
  end process;

END;



Up Counter



library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;


entity counter is 
  port(C, S : in  std_logic; 
        Q : out std_logic_vector(3 downto 0)); 

end counter;
architecture archi of counter is 
  signal tmp: std_logic_vector(3 downto 0); 
  begin 
    process (C) 
      begin 
        if (C'event and C='1') then 

          if (S='1') then
            tmp = "0000"; 
          else 
            tmp = tmp + 1; 

          end if; 
        end if; 
    end process; 
    Q = tmp; 
end archi;

Up Counter Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY downtest IS
END downtest;

ARCHITECTURE behavior OF downtest IS

   -- Component Declaration for the Unit Under Test (UUT)

   COMPONENT counter
   PORT(
        C : IN  std_logic;
        S : IN  std_logic;
        Q : OUT  std_logic_vector(3 downto 0)
       );
   END COMPONENT;
  

  --Inputs
  signal C : std_logic := '0';
  signal S : std_logic := '0';

 --Outputs
  signal Q : std_logic_vector(3 downto 0);
  -- No clocks detected in port list. Replace  below with
  -- appropriate port name

BEGIN

 -- Instantiate the Unit Under Test (UUT)
  uut: counter PORT MAP (
         C => C,
         S => S,
         Q => Q
       );

  -- Clock process definitions


  -- Stimulus process
  stim_proc: process
  begin  
     -- hold reset state for 100 ns.
     wait for 100 ns; 
  C<='0';
  S<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  S<='1';
  up_down<='1';
  wait for 100 ns; 
  C<='0';
  S<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  S<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='1';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  s<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  s<='0';
  up_down<='0';
  



   

     -- insert stimulus here

     wait;
  end process;

END;





Up Down counter



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity counter is
  port(C, CLR, up_down : in std_logic;
        Q : out std_logic_vector(3 downto 0));

end counter;


architecture archi of counter is
  signal tmp: std_logic_vector(3 downto 0);
  begin 
    process (C, CLR)
      begin

        if (CLR='1') then
          tmp = "0000";
        elsif (C'event and C='1') then

          if (up_down='1') then
            tmp = tmp + 1;
          else
            tmp = tmp - 1;

          end if;
        end if;
    end process;
    Q = tmp;
end archi;





Updown counter Testbench:
                                                                    
                                                                   
                                                                   
                                       
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY letusc IS
END letusc;

ARCHITECTURE behavior OF letusc IS

   -- Component Declaration for the Unit Under Test (UUT)

   COMPONENT counter
   PORT(
        C : IN  std_logic;
        CLR : IN  std_logic;
        up_down : IN  std_logic;
        Q : OUT  std_logic_vector(3 downto 0)
       );
   END COMPONENT;
  

  --Inputs
  signal C : std_logic := '0';
  signal CLR : std_logic := '0';
  signal up_down : std_logic := '0';

 --Outputs
  signal Q : std_logic_vector(3 downto 0);
  -- No clocks detected in port list. Replace  below with
  -- appropriate port name

--  constant _period : time := 10 ns;

BEGIN

 -- Instantiate the Unit Under Test (UUT)
  uut: counter PORT MAP (
         C => C,
         CLR => CLR,
         up_down => up_down,
         Q => Q
       );



  -- Stimulus process
  stim_proc: process
  begin  
     -- hold reset state for 100 ns.
     wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='1';
  up_down<='1';
  wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
   wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='1';
  up_down<='0';
   wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
   wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
   wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
   wait for 100 ns; 
  C<='0';
  CLR<='0';
  up_down<='0';
  wait for 100 ns; 
  C<='1';
  CLR<='0';
  up_down<='0';
  
  
   

     -- insert stimulus here

     wait;
  end process;

END;










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